FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 100: Sample Window
Symbol
T
Sampling Error at Receiver Pins
SAMP
T
Sampling Error at Receiver Pins using BUFIO
SAMP_BUFIO
Notes:
1.
This parameter indicates the total sampling error of Virtex-5 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
2.
This parameter indicates the total sampling error of Virtex-5 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Table 101: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
T
/T
Setup/Hold of I/O clock
PSCS
PHCS
Pin-to-Pin Clock-to-Out Using BUFIO
T
Clock-to-Out of I/O clock
ICKOFCS
Revision History
The following table shows the revision history for this document.
Date
Version
04/14/06
1.0
Initial Xilinx release.
05/12/06
1.1
• First version posted to the Xilinx website. Minor typographical edits. Revised design software version on
page
30.
• Revised T
• Revised TDSPCKO in
05/24/06
1.2
Added register-to-register parameters to
08/04/06
1.3
• Added V
• Added HSTL_I_12 and LVCMOS12 to
• Removed pin-to-pin performance (Table 12). Updated and added values to register-register
performance
• Added values to
• Updated the speed specification version above
• Added to
SSTL18_II_T_DCI.
• Revised F
• In
Table
pointing to Architecture Wizard.
• Removed Note 2 on
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
(1)
(2)
Description
Revision
in
Table 64, page
44.
IDELAYRESOLUTION
Table 69, page
48.
Table
52.
, V
, and C
values to
Table
3.
DRINT
DRI
IN
Table 7
and renumbered the notes.
Table 52
(was Table 13).
Table
53.
Table
Table 56
the I/O standards: HSTL_II_T_DCI, HSTL_II_T_DCI_18, SSTL2_II_T_DCI, and
values in
Table
68, and RDWR_B Setup/Hold values in
MAX
74, changed F
, removed T
VCOMAX
LOCKMIN
Table
88.
www.xilinx.com
Speed Grade
Device
-3
-2
-1
All
450
500
550
All
350
400
450
Speed Grade
-3
-2
–0.56
–0.54
–0.54
1.59
1.72
1.91
4.42
4.82
5.40
54.
Table
70.
, and revised T
values, also removed note
LOCKMAX
Units
ps
ps
Units
-1
ns
ns
85