PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 13

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Name
P_IRDY_L
P_TRDY_L
P_DEVSEL_L
P_STOP_L
P_LOCK_L
P_IDSEL
P_PERR_L
P_SERR_L
P_REQ_L
P_GNT_L
P_RESET_L
Pin #
97
99
100
101
102
83
104
105
69
68
64
Page 13 of 90
Type
STS
STS
STS
STS
STS
OD
TS
I
I
I
I
Description
Primary IRDY (Active LOW). Driven by the initiator
of a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-asserted state
for one cycle.
Primary TRDY (Active LOW). Driven by the target of
a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated,
it is driven to a de-asserted state for one cycle.
Primary Device Select (Active LOW). Asserted by the
target indicating that the device is accepting the
transaction. As a master, PI7C8152x waits for the
assertion of this signal within 5 cycles of P_FRAME_L
assertion; otherwise, terminate with master abort. Before
tri-stated, it is driven to a
de-asserted state for one cycle.
Primary STOP (Active LOW). Asserted by the target
indicating that the target is requesting the initiator to stop
the current transaction. Before tri-stated, it is driven to a
de-asserted state for one cycle.
Primary LOCK (Active LOW). Asserted by an
initiator, one clock cycle after the first address phase of a
transaction, attempting to perform an operation that may
take more than one PCI transaction to complete.
Primary ID Select. Used as a chip select line for Type
0 configuration access to PI7C8152x configuration
space.
Primary Parity Error (Active LOW). Asserted when
a data parity error is detected for data received on the
primary interface. Before being tri-stated, it is driven to
a de-asserted state for one cycle.
Primary System Error (Active LOW). Can be driven
LOW by any device to indicate a system error condition.
PI7C8152x drives this pin on:
!
!
!
!
!
!
!
!
!
This signal requires an external pull-up resistor for
proper operation.
Primary Request (Active LOW): This is asserted by
PI7C8152x to indicate that it wants to start a transaction
on the primary bus. PI7C8152x de-asserts this pin for at
least 2 PCI clock cycles before asserting it again.
Primary Grant (Active LOW): When asserted,
PI7C8152x can access the primary bus. During idle and
P_GNT_L asserted, PI7C8152x will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
Primary RESET (Active LOW): When P_RESET_L is
active, all PCI signals should be asynchronously tri-
stated.
Address parity error
Posted write data parity error on target bus
Secondary S_SERR_L asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B