PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 60

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8
8.1
8.2
8.2.1
PCI BUS ARBITRATION
PI7C8152x must arbitrate for use of the primary bus when forwarding upstream
transactions. Also, it must arbitrate for use of the secondary bus when forwarding
downstream transactions. The arbiter for the primary bus resides external to PI7C8152x,
typically on the motherboard. For the secondary PCI bus, PI7C8152x implements an
internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead.
This chapter describes primary and secondary bus arbitration.
PRIMARY PCI BUS ARBITRATION
PI7C8152x implements a request output pin, P_REQ_L, and a grant input pin, P_GNT_L,
for primary PCI bus arbitration. PI7C8152x asserts P_REQ_L when forwarding
transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at least
one pending transaction resides in the queues in the upstream direction, either posted write
data or delayed transaction requests, PI7C8152x keeps P_REQ_L asserted. However, if a
target retry, target disconnect, or a target abort is received in response to a transaction
initiated by PI7C8152x on the primary PCI bus, PI7C8152x de-asserts P_REQ_L for two
PCI clock cycles.
For all cycles through the bridge, P_REQ_L is not asserted until the transaction request has
been completely queued. When P_GNT_L is asserted LOW by the primary bus arbiter
after PI7C8152x has asserted P_REQ_L, PI7C8152x initiates a transaction on the primary
bus during the next PCI clock cycle. When P_GNT_L is asserted to PI7C8152x when
P_REQ_L is not asserted, PI7C8152x parks P_AD, P_CBE, and P_PAR by driving them to
valid logic levels. When the primary bus is parked at PI7C8152x and PI7C8152x has a
transaction to initiate on the primary bus, PI7C8152x starts the transaction if P_GNT_L
was asserted during the previous cycle.
SECONDARY PCI BUS ARBITRATION
PI7C8152x implements an internal secondary PCI bus arbiter. This arbiter supports four
external masters on the secondary bus in addition to PI7C8152x. The internal arbiter can be
disabled, and an external arbiter can be used instead for secondary bus arbitration.
SECONDARY BUS ARBITRATION USING THE INTERNAL
ARBITER
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN_L, must be tied
LOW. PI7C8152x has four secondary bus request input pins, S_REQ_L[3:0], and has four
secondary bus output grant pins, S_GNT_L[3:0], to support external secondary bus
masters.
The secondary bus request and grant signals are connected internally to the arbiter and are
not brought out to external pins when S_CFN_L is LOW.
The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each
set taking care of 4 requests / grants. Each set of masters can be assigned to a high priority
Page 60 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B