PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 74

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.1.21
12.1.22
12.1.23
12.1.24
12.1.25
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS
REGISTER – OFFSET 28h
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS
REGISTER – OFFSET 2Ch
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
ECP POINTER REGISTER – OFFSET 34h
Bit
31:20
Bit
31:0
Bit
31:0
Bit
15:0
Bit
31:16
Bit
7:0
Function
Prefetchable
Memory Limit
Address [31:20]
Function
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
Function
Prefetchable
Memory Limit
Address, Upper
32-bits [63:32]
Function
I/O Base
Address, Upper
16-bits [31:16]
Function
I/O Limit
Address, Upper
16-bits [31:16]
Function
Enhanced
Capabilities Port
Pointer
Type
R/W
Type
R/W
Type
R/W
Type
R/W
Type
R/W
Type
R/W
Page 74 of 90
Description
Defines the top address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be
FFFFFh. The memory limit upper 32 bits register contains the upper
half of the limit address.
Description
Defines the upper 32-bits of a 64-bit bottom address of an address
range for the bridge to determine when to forward memory read and
write transactions from one interface to the other.
Reset to 0
Description
Defines the upper 32-bits of a 64-bit top address of an address range
for the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
Description
Defines the upper 16-bits of a 32-bit bottom address of an address
range for the bridge to determine when to forward I/O transactions
from one interface to the other.
Reset to 0
Description
Defines the upper 16-bits of a 32-bit top address of an address range
for the bridge to determine when to forward I/O transactions from
one interface to the other.
Reset to 0
Description
Enhanced capabilities port offset pointer. Read as DCh to indicate
that the first item resides at that configuration offset.
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B