PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 24

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.7.3
3.7.4
Table 3-4 READ PREFETCH ADDRESS BOUNDARIES
Table 3-5 READ TRANSACTION PREFETCHING
transactions. If these locations are mapped in memory space, use the memory read
command and map the target into non-prefetchable (memory-mapped I/O) memory space
to use non-prefetching behavior.
READ PREFETCH ADDRESS BOUNDARIES
PI7C8152x imposes internal read address boundaries on read prefetched data. When a read
transaction reaches one of these aligned address boundaries, the PI7C8152x stops pre-
fetched data, unless the target signals a target disconnect before the read prefetched
boundary is reached. When PI7C8152x finishes transferring this read data to the initiator, it
returns a target disconnect with the last data transfer, unless the initiator completes the
transaction before all pre-fetched read data is delivered. Any leftover prefetched data is
discarded.
Prefetchable read transactions in flow-through mode prefetch to the nearest aligned 4KB
address boundary, or until the initiator de-asserts FRAME_L. Section 3.7.6 describes flow-
through mode during read operations.
Table 3-4shows the read prefetch address boundaries for read transactions during non-
flow-through mode.
DELAYED READ REQUESTS
PI7C8152x treats all read transactions as delayed read transactions, which means that the
read request from the initiator is posted into a delayed transaction queue. Read data from
- does not matter if it is prefetchable or non-prefetchable
* don’t care
See Section 4.3 for detailed information about prefetchable and non-prefetchable address spaces.
Type of Transaction
Configuration Read
I/O Read
Memory Read
Memory Read
Memory Read
Memory Read Line
Memory Read Line
Memory Read Multiple
Memory Read Multiple
Type of Transaction
I/O Read
Configuration Read
Memory Read
Memory Read Line
Memory Read Multiple
Address Space
-
-
Non-Prefetchable
Prefetchable
Prefetchable
-
-
-
-
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Read Behavior
Prefetching never allowed
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Upstream: Prefetching used
Prefetching always used
Prefetching always used
Cache
(CLS)
*
*
*
CLS = 0 or 16
CLS = 1, 2, 4, 8
CLS = 0 or 16
CLS = 1, 2, 4, 8
CLS = 0 or 16
CLS = 1, 2, 4, 8
Line
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
Size
ADVANCE INFORMATION
PI7C8152A & PI7C8152B
Prefetch Address Boundary
One DWORD (no prefetch)
One DWORD (no prefetch)
One DWORD (no prefetch)
16-DWORD aligned address
boundary
Cache line address boundary
16-DWORD aligned address
boundary
Cache line boundary
Queue full
Second cache line boundary