PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 23

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6.6
3.7
3.7.1
3.7.2
FAST BACK-TO-BACK WRITE TRANSACTIONS
PI7C8152x is capable of decoding and forwarding fast back-to-back write transactions.
When PI7C8152x cannot accept the second transaction because of buffer space limitations,
it returns a target retry to the initiator. The fast back-to-back enable bit must be set in the
command register for upstream write transactions, and in the bridge control register for
downstream write transactions.
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C8152x.
Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 3-5
shows the read behavior, prefetchable or non-prefetchable, for each
type of read operation.
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C8152x performs
speculative DWORD reads, transferring data from the target before it is requested from the
initiator. This behavior allows a prefetchable read transaction to consist of multiple data
transfers. However, byte enable bits cannot be forwarded for all data phases as is done for
the single data phase of the non-prefetchable read transaction. For prefetchable read
transactions, PI7C8152x forces all byte enable bits to be on for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions,
as well as for memory read transactions that fall into prefetchable memory space.
The amount of data that is prefetched depends on the type of transaction. The amount of
prefetching may also be affected by the amount of free buffer space available in
PI7C8152x, and by any read address boundaries encountered.
Prefetching should not be used for those read transactions that have side effects in the
target device, that is, control and status registers, FIFO’s, and so on. The target device’s
base address register or registers indicate if a memory address region is prefetchable.
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C8152x requests one
and only one DWORD from the target and disconnects the initiator after delivery of the
first DWORD of read data. Unlike prefetchable read transactions, PI7C8152x forwards the
read byte enable information for the data phase.
Non-prefetchable behavior is used for I/O and configuration read transactions,
as well as for memory read transactions that fall into non-prefetchable memory space.
If extra read transactions could have side effects, for example, when accessing a FIFO, use
non-prefetchable read transactions to those locations. Accordingly, if it is important to
retain the value of the byte enable bits during the data phase, use non-prefetchable read
Page 23 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B