PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 86

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2
13.2.1
13.2.2
13.2.3
13.2.4
ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
MASTER ABORT
Master abort indicates that when PI7C8152x acts as a master and receives no response (i.e.,
no target asserts DEVSEL_L or S_DEVSEL_L) from a target, the bridge de-asserts
FRAME_L and then de-asserts IRDY_L.
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR,
and S_PAR signals. Parity should be even (i. e. an even number of‘1’s) across AD, CBE,
and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For
reads, even parity must be generated using the initiators CBE signals combined with the
read data. Again, the PAR signal corresponds to read data from the previous data phase
cycle.
REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the
P_SERR_L signal by asserting P_SERR_L for one cycle and then tri-stating two cycles
after the bad address. P_SERR_L can only be asserted if bit 6 and 8 in the Command
Register are both set to 1. For write data phases, a parity error should be reported by
asserting the P_PERR_L signal two cycles after the data phase and should remain asserted
for one cycle when bit 6 in the Command register is set to a 1.
The target reports any type of data parity errors during write cycles, while the master
reports data parity errors during read cycles.
Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim
the bus (P_DEVSEL_L remains inactive) and the cycle will then terminate with a Master
Abort. When the bridge is acting as master, a address parity error during a read cycle
results in the bridge master initiating a Master Abort.
SECONDARY IDSEL MAPPING
When PI7C8152x detects a Type 1 configuration transaction for a device connected to
the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream
interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a device
number. This is translated to S_AD[31:16] by PI7C8152x.
Initiator
Master on Secondary
Target
Target not on Primary
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Response
PI7C8152x does not respond.
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B