PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 56

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4
SYSTEM ERROR (SERR_L) REPORTING
PI7C8152x uses the P_SERR_L signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section 6.2.3.
Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the
following conditions apply:
!
!
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8152x asserts
P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the
SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8152x
also sets the received system error bit in the secondary status register.
PI7C8152x also conditionally asserts P_SERR_L for any of the following reasons:
!
!
!
!
!
!
!
The device-specific P_SERR_L status register reports the reason for the assertion of
P_SERR_L. Most of these events have additional device-specific disable bits in the
P_SERR_L event disable register that make it possible to mask out P_SERR_L assertion
for specific events. The master timeout condition has a SERR_L enable bit for that event in
the bridge control register and therefore does not have a device-specific disable bit.
2
3
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
For PI7C8152x to assert P_SERR_L for any reason, the SERR_L enable bit must be
set in the command register.
Whenever PI7C8152x asserts P_SERR_L, PI7C8152x must also set the signaled
system error bit in the status register.
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
received)
Parity error reported on target bus during posted write transaction (see previous
section)
Delayed write data discarded after 2
received)
Delayed read data cannot be transferred from target after 2
target retries received)
Master timeout on delayed transaction
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24
(default) attempts to deliver (2
(default) attempts to deliver (2
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
24
PI7C8152A & PI7C8152B
(default) attempts (2
24
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target retries
target retries
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