PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 50

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.4
!
!
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
!
!
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the following
events occur:
!
!
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C8152x responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
!
!
!
!
PI7C8152x sets the secondary interface parity-error-detected bit in the secondary
status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
PI7C8152x asserts P_PERR_L two cycles after the data transfer, if the following are
both true:
PI7C8152x completes the transaction normally.
PI7C8152x asserts S_PERR_L two cycles after the data transfer, if the following are
both true:
PI7C8152x completes the transaction normally.
PI7C8152x asserts P_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
PI7C8152x sets the parity error detected bit in the status register of the primary
interface.
PI7C8152x captures and forwards the bad parity condition to the secondary bus.
PI7C8152x completes the transaction normally.
!
!
!
!
The parity-error-response bit is set in the command register of the primary
interface.
The parity-error-response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
The parity error response bit is set in the bridge control register of the
secondary interface.
Page 50 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B