PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 46

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1
condition on one bus to the other bus, along with address and data. PI7C8152x always
attempts to be transparent when reporting errors, but this is not always possible, given the
presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C8152x implements the following:
!
!
!
This chapter provides detailed information about how PI7C8152x handles errors.
It also describes error status reporting and error operation disabling.
ADDRESS PARITY ERRORS
PI7C8152x checks address parity for all transactions on both buses, for all address and all
bus commands. When PI7C8152x detects an address parity error on the primary interface,
the following events occur:
!
!
!
When PI7C8152x detects an address parity error on the secondary interface, the following
events occur:
!
!
!
PERR_L and SERR_L signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR_L event disable register
If the parity error response bit is set in the command register, PI7C8152x does not
claim the transaction with P_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8152x proceeds normally
and accepts the transaction if it is directed to or across PI7C8152x.
PI7C8152x sets the detected parity error bit in the status register.
PI7C8152x asserts P_SERR_L and sets signaled system error bit in the status register,
if both the following conditions are met:
If the parity error response bit is set in the bridge control register, PI7C8152x does not
claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8152x proceeds normally
and accepts transaction if it is directed to or across PI7C8152x.
PI7C8152x sets the detected parity error bit in the secondary status register.
PI7C8152x asserts P_SERR_L and sets signaled system error bit in status register, if
both of the following conditions are met:
!
!
!
!
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the command register.
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register.
Page 46 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B