PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 33

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.9.3.1
3.9.3.2
Table 3-7 DELAYED WRITE TARGET TERMINATION RESPONSE
Table 3-8 RESPONSE TO POSTED WRITE TARGET TERMINATION
PI7C8152x handles these terminations in different ways, depending on the type of
transaction being performed.
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8152x initiates a delayed write transaction, the type of target termination
received from the target can be passed back to the initiator. Table 3-7 shows the response
to each type of target termination that occurs during a delayed write transaction.
PI7C8152x repeats a delayed write transaction until one of the following conditions is met:
!
!
!
PI7C8152x makes 2
target retry.
After the PI7C8152x makes 2
the target bus, PI7C8152x asserts P_SERR_L if the SERR_L enable bit (bit 8 of command
register for the secondary bus) is set and the delayed-write-non-delivery bit is not set. The
delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h).
PI7C8152x will report system error. See Section 6.4 for a description of system error
conditions.
POSTED WRITE TARGET TERMINATION RESPONSE
When PI7C8152x initiates a posted write transaction, the target termination cannot
be passed back to the initiator. Table 3-8 shows the response to each type of target
termination that occurs during a posted write transaction.
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
PI7C8152x completes at least one data transfer.
PI7C8152x receives a master abort.
PI7C8152x receives a target abort.
24
(default) or 2
Response
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target retry to initiator. Continue write attempts to target
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target abort to initiator. Set received target abort bit in target interface
status register. Set signaled target abort bit in initiator interface status register.
Repsonse
No additional action.
Repeating write transaction to target.
Initiate write transaction for delivering remaining posted write data.
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
24
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(default) attempts of the same delayed write trans-action on
32
(maximum) write attempts resulting in a response of
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B