PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 48

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.3
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PI7C8152x returns to the initiator the data and parity that was received from the target.
When the initiator detects a parity error on this read data and is enabled to report it, the
initiator asserts PERR_L two cycles after the data transfer occurs. It is assumed that the
initiator takes responsibility for handling a parity error condition; therefore, when
PI7C8152x detects PERR_L asserted while returning read data to the initiator, PI7C8152x
does not take any further action and completes the transaction normally.
DELAYED WRITE TRANSACTIONS
When PI7C8152x detects a data parity error during a delayed write transaction, the initiator
drives data and data parity, and the target checks parity and conditionally asserts PERR_L.
For delayed write transactions, a parity error can occur at the following times:
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When a delayed write transaction is normally queued, the address, command, address
parity, data, byte enable bits, and data parity are all captured and a target retry is returned to
the initiator. When PI7C8152x detects a parity error on the write data for the initial delayed
write request transaction, the following events occur:
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PI7C8152x asserts P_PERR_L two cycles following the data transfer, if the primary
interface parity error response bit is set in the command register.
PI7C8152x sets the detected parity error bit in the primary status register.
PI7C8152x sets the data parity detected bit in the primary status register, if the primary
interface parity-error-response bit is set in the command register.
PI7C8152x forwards the bad parity with the data back to the initiator on the secondary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
secondary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
PI7C8152x completes the transaction normally.
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When PI7C8152x completes the delayed write transaction to the target
If the parity-error-response bit corresponding to the initiator bus is set, PI7C8152x
asserts TRDY_L to the initiator and the transaction is not queued. If multiple data
phases are requested, STOP_L is also asserted to cause a target disconnect. Two cycles
after the data transfer, PI7C8152x also asserts PERR_L.
If the parity-error-response bit is not set, PI7C8152x returns a target retry.
It queues the transaction as usual. PI7C8152x does not assert PERR_L.
In this case, the initiator repeats the transaction.
PI7C8152x sets the detected-parity-error bit in the status register corresponding to the
initiator bus, regardless of the state of the parity-error-response bit.
Page 48 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B