PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 79

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.1.31
12.1.32
SECONDARY BUS ARBITER PREEMPTION CONTROL
REGISTER – OFFSET 4Ch
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h
Bit
31:28
Bit
0
1
2
3
Function
Secondary bus
arbiter
preemption
contorl
Function
Reserved
Posted Write
Parity Error
Posted Write
Non-Delivery
Target Abort
During Posted
Write
Type
R/W
Type
R/O
R/W
R/W
R/W
Page 79 of 90
Description
Controls the number of clock cycles after frame is asserted before
preemption is enabled.
1xxx: Preemption off
0000: Preemption enabled after 0 clock cycles after FRAME asserted
0001: Preemption enabled after 1 clock cycle after FRAME asserted
0010: Preemption enabled after 2 clock cycles after FRAME asserted
0011: Preemption enabled after 4 clock cycles after FRAME asserted
0100: Preemption enabled after 8 clock cycles after FRAME asserted
0101: Preemption enabled after 16 clock cycles after FRAME
asserted
0110: Preemption enabled after 32 clock cycles after FRAME
asserted
0111: Preemption enabled after 64 clock cycles after FRAME
asserted
Description
Reserved. Returns 0 when read. Reset to 0
Controls PI7C8152x’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
1: P_SERR_L is not asserted if this event occurs.
Reset to 0
Controls PI7C8152x’s ability to assert P_SERR_L when it is unable
to transfer delayed write data after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8152x’s ability to assert P_SERR_L when it receives a
target abort when attempting to deliver posted write data.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
24
PI7C8152A & PI7C8152B
attempts.
24
attempts.