PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 47

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2
6.2.1
6.2.2
DATA PARITY ERRORS
When forwarding transactions, PI7C8152x attempts to pass the data parity condition from
one interface to the other unchanged, whenever possible, to allow the master and target
devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C8152x.
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C8152x detects a data parity error during a Type 0 configuration write
transaction to PI7C8152x configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C8152x asserts
P_TRDY_L and writes the data to the configuration register. PI7C8152x also asserts
P_PERR_L. If the parity error response bit is not set, PI7C8152x does not assert
P_PERR_L.
PI7C8152x sets the detected parity error bit in the status register, regardless of the state of
the parity error response bit.
READ TRANSACTIONS
When PI7C8152x detects a parity error during a read transaction, the target drives data and
data parity, and the initiator checks parity and conditionally asserts PERR_L.
For downstream transactions, when PI7C8152x detects a read data parity error on the
secondary bus, the following events occur:
!
!
!
!
!
For upstream transactions, when PI7C8152x detects a read data parity error on the primary
bus, the following events occur:
PI7C8152x asserts S_PERR_L two cycles following the data transfer, if the secondary
interface parity error response bit is set in the bridge control register.
PI7C8152x sets the detected parity error bit in the secondary status register.
PI7C8152x sets the data parity detected bit in the secondary status register, if the
secondary interface parity error response bit is set in the bridge control register.
PI7C8152x forwards the bad parity with the data back to the initiator on the primary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
primary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
PI7C8152x completes the transaction normally.
Page 47 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B