PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 88

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4
14.5
14.6
1. See Figure 14-1 PCI Signal Timing Measurement Conditions.
2. All primary interface signals are synchronized to P_CLK. All secondary interface
signals are synchronized to S_CLKIN.
3. Point-to-point signals are P_REQ_L, S_REQ_L[3:0], P_GNT_L, and S_GNT_L[3:0].
Bused signals are P_AD, P_CBE_L, P_PAR, P_PERR_L, P_SERR_L, P_FRAME_L,
P_IRDY_L, P_TRDY_L, P_LOCK_L, P_DEVSEL_L, P_STOP_L, P_IDSEL, S_AD,
S_CBE_L, S_PAR, S_PERR_L, S_SERR_L, S_FRAME_L, S_IRDY_L, S_TRDY_L,
S_LOCK_L, S_DEVSEL_L, and S_STOP_L.
4. REQ_L signals have a setup of 10 and GNT_L signals have a setup of 12.
66MHZ PCI SIGNALING TIMING
33MHZ PCI SIGNALING TIMING
RESET TIMING
Figure 14-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS
Symbol
Tsu
Tsu(ptp)
Th
Tval
Tval(ptp)
Ton
Toff
Symbol
T
T
T
T
T
Symbol
T
T
T
T
T
Symbol
T
T
T
T
T
T
SKEW
DELAY
CYCLE
HIGH
LOW
SKEW
DELAY
CYCLE
HIGH
LOW
RST
RST-CLK
RST-OFF
SRST
SRST-ON
DRST
Parameter
SKEW among S_CLKOUT[4:0]
DELAY between PCLK and S_CLKOUT[4:0]
PCLK, S_CLKOUT[4:0] cycle time
PCLK, S_CLKOUT[4:0] HIGH time
PCLK, S_CLKOUT[4:0] LOW time
Parameter
SKEW among S_CLKOUT[4:0]
DELAY between PCLK and S_CLKOUT[4:0]
PCLK, S_CLKOUT[4:0] cycle time
PCLK, S_CLKOUT[4:0] HIGH time
PCLK, S_CLKOUT[4:0] LOW time
Parameter
P_RESET_L active time after power stable
P_RESET_L active time after P_CLK stable
P_RESET_L active-to-output float delay
S_RESET_L active after P_RESET_L assertion
S_RESET_L active time after S_CLKIN stable
S_RESET_L deassertion after P_RESET_L deassertion
Float to active delay
Active to float delay
Parameter
Input setup time to CLK – bused signals
Input setup time to CLK – point-to-point
Input signal hold time from CLK
CLK to signal valid delay – bused signals
CLK to signal valid delay – point-to-point
1,2
1,2
Page 88 of 90
1,2
1,2,3
1,2,3
1,2,3
1,2,3
Condition
20pF load
Condition
20pF load
Min.
3
5
0
2
2
2
-
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
66 MHz
PI7C8152A & PI7C8152B
Max.
-
-
-
6
6
-
14
Min.
0
2.82
15
6
6
Min.
0
2.82
30
11
11
Min.
1
100
-
-
100
20
Min.
7
10, 12
0
2
2
2
-
Max.
0.250
4.22
30
Max.
0.250
4.22
33 MHz
Max.
-
-
40
40
-
25
4
Max.
-
-
-
11
12
-
28
Units
ns
Units
ns
Units
us
us
ns
ns
us
cycles
Units
ns