PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 51

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Similarly, during upstream posted write transactions, when PI7C8152x responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following events
occur:
!
!
!
!
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR_L, the following events occur:
!
!
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR_L, the following events occur:
!
!
PI7C8152x asserts S_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
PI7C8152x sets the parity error detected bit in the status register of the secondary
interface.
PI7C8152x captures and forwards the bad parity condition to the primary bus.
PI7C8152x completes the transaction normally.
PI7C8152x sets the data parity detected bit in the status register of secondary interface,
if the parity error response bit is set in the bridge control register of the secondary
interface.
PI7C8152x asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
PI7C8152x sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
PI7C8152x asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
!
!
!
!
!
!
!
The SERR_L enable bit is set in the command register.
The posted write parity error bit of P_SERR_L event disable register is not
set.
The parity error response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C8152x has not detected the parity error on the primary (initiator) bus
which the parity error is not forwarded from the primary bus to the
secondary bus.
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register of the
secondary interface.
Page 51 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B