PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 26

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.7.7
3.8
transaction before all read data has been transferred, the remaining read data left in data
buffers is discarded.
When the master repeats the transaction and starts transferring prefetchable read data from
data buffers while the read transaction on the target bus is still in progress and before a read
boundary is reached on the target bus, the read transaction starts operating in flow-through
mode. Because data is flowing through the data buffers from the target to the initiator, long
read bursts can then be sustained. In this case, the read transaction is allowed to continue
until the initiator terminates the transaction, or until an aligned 4KB address boundary is
reached, or until the buffer fills, whichever comes first. When the buffer empties,
PI7C8152x reflects the stalled condition to the initiator by disconnecting the initiator with
data. The initiator may retry the transaction later if data are needed. If the initiator does not
need any more data, the initiator will not continue the disconnected transaction. In this
case, PI7C8152x will start the master timeout timer. The remaining read data will be
discarded after the master timeout timer expires. To provide better latency, if there are any
other pending data for other transactions in the RDB (Read Data Buffer), the remaining
read data will be discarded even though the master timeout timer has not expired.
PI7C8152x implements a master timeout timer that starts counting when the delayed read
completion is at the head of the delayed transaction queue, and the read data is at the head
of the read data queue. The initial value of this timer is programmable through
configuration transaction. If the initiator does not repeat the read transaction and before the
master timeout timer expires (2
read data from its queues. PI7C8152x also conditionally asserts P_SERR_L (see Section
6.4).
PI7C8152x has the capability to post multiple delayed read requests, up to a maximum of
four in each direction. If an initiator starts a read transaction that matches the address and
read command of a read transaction that is already queued, the current read command is not
posted as it is already contained in the delayed transaction queue.
See Section 5 for a discussion of how delayed read transactions are ordered when crossing
PI7C8152x.
FAST BACK-TO-BACK READ TRANSACTION
PI7C8152x is capable to decode fast back-to-back read transactions on both primary and
secondary. PI7C8152x cannot generate fast back-to-back read transactions on both the
secondary and primary even if bit[23] of offset 3Ch is set to ‘1’ or bit[9] of offset 04h is
set to ‘1’.
CONFIGURATION TRANSACTIONS
Configuration transactions are used to initialize a PCI system. Every PCI device has a
configuration space that is accessed by configuration commands. All registers are
accessible in configuration space only.
In addition to accepting configuration transactions for initialization of its own
configuration space, the PI7C8152x also forwards configuration transactions for device
initialization in hierarchical PCI systems, as well as for special cycle generation.
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default), PI7C8152x discards the read transaction and
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B