PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 76

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.1.28
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
Bit
22
23
24
25
26
27
31-28
Bit
0
Function
Secondary
Interface Reset
Fast Back-to-
Back Enable
Primary Master
Timeout
Secondary
Master Timeout
Master Timeout
Status
Discard Timer
P_SERR_L
enable
Reserved
Function
Reserved
Type
R/W
R/W
R/W
R/W
R/WC
R/W
R/O
Type
R/O
Page 76 of 90
Description
Reserved. Returns 0 when read. Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Description
Controls the assertion of S_RESET_L signal pin on the secondary
interface
0: does not force the assertion of S_RESET_L pin
1: forces the assertion of S_RESET_L
Reset to 0
Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the secondary interface.
0: does not generate fast back-to-back transactions on the secondary
1: enables fast back-to-back transaction generation on the secondary
Reset to 0
Determines the maximum number of PCI clock cycles the
PI7C8152x waits for an initiator on the primary interface to repeat a
delayed transaction request.
0: Primary discard timer counts 2
1: Primary discard timer counts 2
Reset to 0
Determines the maximum number of PCI clock cycles the
PI7C8152x waits for an initiator on the primary interface to repeat a
delayed transaction request.
0: Primary discard timer counts 2
1: Primary discard timer counts 2
Reset to 0
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
Reset to 0
This bit is set to 1 and P_SERR_L is asserted when either the
primary discard timer or the secondary discard timer expire.
0: P_SERR_L is not asserted on the primary interface as a result of
the expiration of either the Primary Discard Timer or the Secondary
Discard Timer.
1: P_SERR_L is asserted on the primary interface as a result of the
expiration of either the Primary Discard Timer or the Secondary
Discard Timer.
Reset to 0
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
15
10
15
10
PCI clock cycles.
PCI clock cycles.
PCI clock cycles.
PCI clock cycles.
PI7C8152A & PI7C8152B