PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 5

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE OF CONTENTS
1
2
3
4
2.1
2.2
2.3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.1
4.2
4.3
INTRODUCTION .............................................................................................................................. 11
SIGNAL DEFINITIONS ................................................................................................................... 12
2.2.1
2.2.3
2.2.4
2.2.5
PCI BUS OPERATION ..................................................................................................................... 17
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.8.1
3.8.2
3.8.3
3.8.4
3.9.1
3.9.2
3.9.3
3.9.4
ADDRESS DECODING..................................................................................................................... 36
4.2.1
4.2.2
4.3.1
4.3.2
S
S
PIN LIST – 160-PIN MQFP.......................................................................................................... 16
TYPES OF TRANSACTIONS ..................................................................................................... 17
SINGLE ADDRESS PHASE........................................................................................................ 18
DUAL ADDRESS PHASE........................................................................................................... 18
DEVICE SELECT (DEVSEL_L) GENERATION....................................................................... 19
DATA PHASE.............................................................................................................................. 19
WRITE TRANSACTIONS .......................................................................................................... 19
READ TRANSACTIONS ............................................................................................................ 23
CONFIGURATION TRANSACTIONS ...................................................................................... 26
TRANSACTION TERMINATION.............................................................................................. 30
ADDRESS RANGES ................................................................................................................... 37
I/O ADDRESS DECODING ........................................................................................................ 37
MEMORY ADDRESS DECODING............................................................................................ 39
IGNAL
IGNALS
PRIMARY BUS INTERFACE SIGNALS .......................................................................... 12
CLOCK SIGNALS ............................................................................................................... 15
MISCELLANEOUS SIGNALS........................................................................................... 15
POWER AND GROUND..................................................................................................... 16
MEMORY WRITE TRANSACTIONS................................................................................ 20
MEMORY WRITE AND INVALIDATE ............................................................................ 21
DELAYED WRITE TRANSACTIONS............................................................................... 21
WRITE TRANSACTION ADDRESS BOUNDARIES....................................................... 22
BUFFERING MULTIPLE WRITE TRANSACTIONS..................................................... 22
FAST BACK-TO-BACK WRITE TRANSACTIONS ......................................................... 23
PREFETCHABLE READ TRANSACTIONS.................................................................... 23
NON-PREFETCHABLE READ TRANSACTIONS.......................................................... 23
READ PREFETCH ADDRESS BOUNDARIES ............................................................... 24
DELAYED READ REQUESTS .......................................................................................... 24
DELAYED READ COMPLETION ON TARGET BUS .................................................... 25
DELAYED READ COMPLETION ON INITIATOR BUS................................................ 25
FAST BACK-TO-BACK READ TRANSACTION ............................................................. 26
TYPE 0 ACCESS TO PI7C8152x ....................................................................................... 27
TYPE 1 TO TYPE 0 CONVERSION .................................................................................. 27
TYPE 1 TO TYPE 1 FORWARDING................................................................................. 29
SPECIAL CYCLES ............................................................................................................. 30
MASTER TERMINATION INITIATED BY PI7C8152x.................................................. 31
MASTER ABORT RECEIVED BY PI7C8152x................................................................. 32
TARGET TERMINATION RECEIVED BY PI7C8152x .................................................. 32
TARGET TERMINATION INITIATED BY PI7C8152x .................................................. 35
I/O BASE AND LIMIT ADDRESS REGISTER................................................................ 38
ISA MODE........................................................................................................................... 38
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 39
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ................. 40
T
........................................................................................................................................ 12
YPES
............................................................................................................................... 12
Page 5 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B