PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 14

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.2
SECONDARY BUS INTERFACE SIGNALS
Name
S_AD[31:0]
S_CBE[3:0]
S_PAR
S_FRAME_L
S_IRDY_L
S_TRDY_L
S_DEVSEL_L
S_STOP_L
S_LOCK_L
Pin #
36, 35, 33, 32, 31,
29, 28, 26, 24, 22,
21, 20, 18, 17, 16,
14, 156, 155, 153,
152, 150, 149,
148, 146, 144,
142, 141, 140,
138, 137, 136, 134
25, 13, 158, 145
2
11
10
9
7
6
5
Page 14 of 90
Type
STS
STS
STS
STS
STS
STS
TS
TS
TS
Description
Secondary Address/Data: Multiplexed address and data
bus. Address is indicated by S_FRAME_L assertion.
Write data is stable and valid when S_IRDY_L is
asserted and read data is stable and valid when
S_IRDY_L is asserted. Data is transferred on rising
clock edges when both S_IRDY_L and S_TRDY_L are
asserted. During bus idle, PI7C8152x drives S_AD to a
valid logic level when S_GNT_L is asserted
respectively.
Secondary Command/Byte Enables: Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. The initiator then drives the byte enables during
data phases. During bus idle, PI7C8152x drives
S_CBE[3:0] to a valid logic level when the internal grant
is asserted.
Secondary Parity: Parity is even across S_AD[31:0],
S_CBE[3:0], and S_PAR (i.e. an even number of 1’s).
S_PAR is an input and is valid and stable one cycle after
the address phase (indicated by assertion of
S_FRAME_L) for address parity. For write data phases,
S_PAR is an input and is valid one clock after
S_IRDY_L is asserted. For read data phase, S_PAR is
an output and is valid one clock after S_TRDY_L is
asserted. Signal S_PAR is tri-stated one cycle after the
S_AD lines are tri-stated. During bus idle, PI7C8152x
drives S_PAR to a valid logic level when the internal
grant is asserted.
Secondary FRAME (Active LOW): Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of S_FRAME_L
indicates the final data phase requested by the initiator.
Before being tri-stated, it is driven to a de-asserted state
for one cycle.
Secondary IRDY (Active LOW): Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the secondary side. Once
asserted in a data phase, it is not de-asserted until the end
of the data phase. Before tri-stated, it is driven to a de-
asserted state for one cycle.
Secondary TRDY (Active LOW): Driven by the target
of a transaction to indicate its ability to complete current
data phase on the secondary side. Once asserted in a
data phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-asserted state
for one cycle.
Secondary Device Select (Active LOW): Asserted by
the target indicating that the device is accepting the
transaction. As a master, PI7C8152x waits for the
assertion of this signal within 5 cycles of S_FRAME_L
assertion; otherwise, terminate with master abort. Before
tri-stated, it is driven to a de-asserted state for one cycle.
Secondary STOP (Active LOW): Asserted by the
target indicating that the target is requesting the initiator
to stop the current transaction. Before tri-stated, it is
driven to a de-asserted state for one cycle.
Secondary LOCK (Active LOW): Asserted by an
initiator, one clock cycle after the first address phase of a
transaction, when it is propagating a locked transaction
downstream. PI7C8152x does not propagate locked
transactions upstream.
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B