PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 18

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.2
3.3
Table 3-1 PCI TRANSACTIONS
•
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SINGLE ADDRESS PHASE
DUAL ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and
the bus command is driven on P_CBE[3:0]. PI7C8152x supports the linear increment
address mode only, which is indicated when the lowest two address bits are equal to zero.
If either of the lowest two address bits is nonzero, PI7C8152x automatically disconnects
the transaction after the first data transfer.
A 64-bit address uses two address phases. The first address phase is denoted by the
asserting edge of FRAME_L. The second address phase always follows on the next clock
cycle.
For a 32-bit interface, the first address phase contains dual address command code on the
CBE_L[3:0] lines, and the low 32 address bits on the AD[31:0] lines. The second address
As indicated in Table 3-1, the following PCI commands are not supported by PI7C8152x:
!
!
!
PI7C8152x neither generates Type 0 configuration transactions on the primary PCI bus
PI7C8152x never initiates a PCI transaction with a reserved command code and, as a
target, PI7C8152x ignores reserved command codes.
PI7C8152x does not generate interrupt acknowledge transactions. PI7C8152x
ignores interrupt acknowledge transactions as a target.
PI7C8152x does not respond to special cycle transactions. PI7C8152x cannot
guarantee delivery of a special cycle transaction to downstream buses because of the
broadcast nature of the special cycle command and the inability to control the
transaction as a target. To generate special cycle transactions on other PCI buses,
either upstream or downstream, Type 1 configuration write must be used.
nor responds to Type 0 configuration transactions on the secondary PCI bus.
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
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Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B
Responds as Target
Primary
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
N
N
Y
Y
N
N
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Secondary
Y
Y