PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 59

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.2
7.3
LOCKED TRANSACTION IN UPSTREAM DIRECTION
PI7C8152x ignores upstream lock and transactions. PI7C8152x will pass these transactions
as normal transactions without lock established.
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, PI7C8152x must
maintain the lock on the target bus for any subsequent locked transactions until the initiator
relinquishes the lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction of a
locked sequence. On subsequent transactions in the sequence, the target retry has no effect
on the status of the lock signal.
An established target lock is maintained until the initiator relinquishes the lock. PI7C8152x
does not know whether the current transaction is the last one in a sequence of locked
transactions until the initiator de-asserts the LOCK_L signal at end of the transaction.
When the last locked transaction is a delayed transaction, PI7C8152x has already
completed the transaction on the target bus. In this example, as soon as PI7C8152x detects
that the initiator has relinquished the LOCK_L signal by sampling it in the de-asserted state
while FRAME_L is de-asserted, PI7C8152x de-asserts the LOCK_L signal on the target
bus as soon as possible. Because of this behavior, LOCK_L may not be de-asserted until
several cycles after the last locked transaction has been completed on the target bus. As
soon as PI7C8152x has de-asserted LOCK_L to indicate the end of a sequence of locked
transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, PI7C8152x de-asserts
LOCK_L on the target bus at the end of the transaction because the lock was relinquished
at the end of the write transaction on the initiator bus.
When PI7C8152x receives a target abort or a master abort in response to a locked delayed
transaction, PI7C8152x returns a target abort or a master abort when the initiator repeats
the locked transaction. The initiator must then de-assert LOCK_L at the end of the
transaction. PI7C8152x sets the appropriate status bits, flagging the abnormal target
termination condition (see Section 3.9). Normal forwarding of unlocked posted and
delayed transactions is resumed.
When PI7C8152x receives a target abort or a master abort in response to a locked posted
write transaction, PI7C8152x cannot pass back that status to the initiator. PI7C8152x
asserts SERR_L on the initiator bus when a target abort or a master abort is received during
a locked posted write transaction, if the SERR_L enable bit is set in the command register.
Signal SERR_L is asserted for the master abort condition if the master abort mode bit is set
in the bridge control register (see Section 6.4).
Page 59 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B