PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 53

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-3 SETTING PRIMARY BUS MASTER DATA PARITY ERROR DETECTED BIT
Table 6-3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
!
!
!
interface. This bit is set under the following conditions:
!
!
!
Secondary
Detected
Error Bit
0
0
0
0
0
1
0
0
0
1
X = don’t care
Primary
Parity Bit
0
0
1
0
0
0
1
0
0
0
1
0
X = don’t care
Table 6-4 shows setting the data parity detected bit in the status register of secondary
PI7C8152x must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
The P_PERR_L signal is detected asserted or a parity error is detected on the primary
bus.
The PI7C8152x must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
The S_PERR_L signal is detected asserted or a parity error is detected on the
secondary bus.
Parity
Data
Transaction Type
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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Direction
Upstream
Direction
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
Was Detected
Was Detected
ADVANCE INFORMATION
PI7C8152A & PI7C8152B
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary /
Primary/
Bits
Bits