PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 54

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-4 SETTING SECONDARY BUS MASTER DATA PARITY ERROR DETECTED BIT
Table 6-5 ASSERTION OF P_PERR_L
Table 6-5 shows assertion of P_PERR_L. This signal is set under the following conditions:
!
!
!
2
Table 6-6 shows assertion of S_PERR_L that is set under the following conditions:
!
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Secondary
Detected
Detected Bit
0
1
0
0
0
1
0
0
0
1
0
0
X= don’t care
P_PERR#
1 (de-asserted)
1
0 (asserted)
1
0
1
1
1
0
0
1
1
X = don’t care
2
PI7C8152x is either the target of a write transaction or the initiator of a read
transaction on the primary bus.
The parity-error-response bit must be set in the command register of primary interface.
PI7C8152x detects a data parity error on the primary bus or detects S_PERR_L
asserted during the completion phase of a downstream delayed write transaction on the
target (secondary) bus.
PI7C8152x is either the target of a write transaction or the initiator of a read
transaction on the secondary bus.
Parity
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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Direction
Downstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
Was Detected
Was Detected
ADVANCE INFORMATION
PI7C8152A & PI7C8152B
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / x
1 / x
x / x
1 / x
x / x
x / x
x / x
1 / x
1 / 1
x / x
x / x
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary /
Primary/
Bits
Bits