PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 65

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11
11.1
11.2
PME_L signals are routed from downstream devices around PCI-to-PCI bridges. PME_L
signals do not pass through PCI-to-PCI bridges.
RESET
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
PRIMARY INTERFACE RESET
PI7C8152x has a reset input, P_RESET_L. When P_RESET_L is asserted, the following
events occur:
!
!
!
P_RESET_L asserting and de-asserting edges can be asynchronous to P_CLK and
S_CLKOUT. PI7C8152x is not accessible during P_RESET_L. After P_RESET_L is de-
asserted, PI7C8152x remains inaccessible for 16 PCI clocks before the first configuration
transaction can be accepted.
SECONDARY INTERFACE RESET
PI7C8152x is responsible for driving the secondary bus reset signals, S_RESET_L.
PI7C8152x asserts S_RESET_L when any of the following conditions are met:
Signal P_RESET_L is asserted. Signal S_RESET_L remains asserted as long as
P_RESET_L is asserted and does not de-assert until P_RESET_L is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RESET_L
remains asserted until a configuration write operation clears the secondary reset bit.
The chip reset bit in the diagnostic / control register is set. When S_RESET_L is
asserted, PI7C8152x immediately tri-states all the secondary PCI interface signals
associated with the secondary port. The S_RESET_L in asserting and de-asserting edges
can be asynchronous to P_CLK. S_RESET_L remains asserted until a configuration write
operation clears the secondary reset bit.
When S_RESET_L is asserted, all secondary PCI interface control signals, including the
secondary grant outputs, are immediately tri-stated. Signals S_AD, S_CBE_L[3:0], S_PAR
are driven low for the duration of S_RESET_L assertion. All posted write and delayed
transaction data buffers are reset. Therefore, any transactions residing inside the buffers at
the time of secondary reset are discarded.
PI7C8152x immediately tri-states all primary PCI interface signals. On the secondary,
S_AD and S_CBE are driven LOW, while other control signals are tri-stated.
PI7C8152x performs a chip reset.
Registers that have default values are reset.
Page 65 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B