PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 62

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2.2
8.2.3
8.2.4
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one
grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and
asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is
busy, that is, S_FRAME_L or S_IRDY_L is asserted, the arbiter can be de-asserted one
grant and asserted another grant during the same PCI clock cycle.
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit
31=0). Time-to-preempt can be programmed to 0, 1, 2, 4, 8, 16, 32, or 64 (default is 0)
clocks.
If the current master occupies the bus and other masters are waiting, the current master will
be preempted by removing its grant (GNT_L) after the next master waits for the time-to-
preempt.
SECONDARY BUS ARBITRATION USING AN EXTERNAL
ARBITER
The internal arbiter is disabled when the secondary bus central function control pin,
S_CFN_L, is tied HIGH. An external arbiter must then be used.
When S_CFN_L is tied HIGH, PI7C8152x reconfigures two pins to be external request and
grant pins. The S_GNT_L[0] pin is reconfigured to be the external request pin because it’s
an output. The S_REQ_L[0] pin is reconfigured to be the external grant pin because it’s an
input. When an external arbiter is used, PI7C8152x uses the S_GNT_L[0] pin to request
the secondary bus. When the reconfigured S_REQ_L[0] pin is asserted LOW after
PI7C8152x has asserted S_GNT_L[0], PI7C8152x initiates a transaction on the secondary
bus one cycle later. If grant is asserted and PI7C8152x has not asserted the request,
PI7C8152x parks AD, CBE and PAR pins by driving them to valid logic levels.
The unused secondary bus grant outputs, S_GNT_L[3:1] are driven HIGH. The unused
secondary bus request inputs, S_REQ_L[3:1], should be pulled HIGH.
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE_L[3:0], and PAR lines to a known value
while the bus is idle. In general, the device implementing the bus arbiter is responsible for
parking the bus or assigning another device to park the bus. A device parks the bus when
the bus is idle, its bus grant is asserted, and the device’s request is not asserted. The AD
and CBE signals should be driven first, with the PAR signal driven one cycle later.
PI7C8152x parks the primary bus only when P_GNT_L is asserted, P_REQ_L is de-
asserted, and the primary PCI bus is idle. When P_GNT_L is de-asserted, PI7C8152x 3-
states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C8152x is
parking the primary PCI bus and wants to initiate a transaction on that bus, then PI7C8152x
can start the transaction on the next PCI clock cycle by asserting P_FRAME_L if
P_GNT_L is still asserted.
Page 62 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B