PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 83

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.1.36
PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h
Bit
7
8
9
10
11
15:12
Bit
15:0
Function
Primary Memory
Write and
Invalidate
Command Alias
Disable
Secondary
Memory Write
and Invalidate
Command Alias
Disable
Enable Long
Request
Enable
Secondary To
Hold Request
Longer
Enable Primary
To Hold Request
Longer
Reserved
Function
Primary Timeout
Type
R/W
R/W
R/W
R/W
R/W
R/O
Type
R/W
Page 83 of 90
Description
Controls PI7C8152x’s detection mechanism for matching non-posted
memory write and invalidate cycles from the initiator on the primary
interface
0: When accepting MEMWI command at the primary interface,
PI7C8152x converts MEMWI to MEMW command on the
destination interface
1: When accepting MEMWI command at the primary interface,
PI7C8152x does not convert MEMWI to MEMW command on the
destination interface
Reset to 0
Controls PI7C8152x’s detection mechanism for matching non-posted
memory write and invalidate cycles from the initiator on the
secondary interface
0: When accepting MEMWI command at the secondary interface,
PI7C8152x converts MEMWI to MEMW command on the
destination interface
1: When accepting MEMWI command at the secondary interface,
PI7C8152x does not convert MEMWI to MEMW command on the
destination interface
Reset to 0
Controls PI7C8152x’s ability to enable long requests for lock cycles
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
Control’s PI7C8152x’s ability to enable the secondary bus to hold
requests longer.
0: internal secondary master will release REQ_L after FRAME_L
assertion
1: internal secondary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Control’s PI7C8152x’s ability to hold requests longer at the Primary
Port.
0: internal Primary master will release REQ_L after FRAME_L
assertion
1: internal Primary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Reserved. Returns 0 when read. Reset to 0.
Description
Primary timeout occurs after 2
Reset to 8000h.
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
15
ADVANCE INFORMATION
PCI clocks.
PI7C8152A & PI7C8152B