PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 42

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4.2
5
5.1
The VGA frame buffer consists of the following memory address range:
000A 0000h–000B FFFFh
Read transactions to frame buffer memory are treated as non-prefetchable. PI7C8152x
requests only a single data transfer from the target, and read byte enable bits are forwarded
to the target bus.
The VGA I/O addresses are in the range of 3B0h–3BBh and 3C0h–3DFh I/O. These I/O
addresses are aliases every 1KB throughout the first 64KB of I/O space. This means that
address bits [5:10] are not decoded and can be any value, while address bits [31:16] must
be all 0’s. VGA BIOS addresses starting at C0000h are not decoded in VGA mode.
VGA SNOOP MODE
PI7C8152x provides VGA snoop mode, allowing for VGA palette write transactions to be
forwarded downstream. This mode is used when a graphics device downstream from
PI7C8152x needs to snoop or respond to VGA palette write transactions. To enable the
mode, set the VGA snoop bit in the command register in configuration space. Note that
PI7C8152x claims VGA palette write transactions by asserting DEVSEL_L in VGA snoop
mode.
When VGA snoop bit is set, PI7C8152x forwards downstream transactions within the
3C6h, 3C8h and 3C9h I/O addresses space. Note that these addresses are also forwarded as
part of the VGA compatibility mode previously described. Again, address bits [15:10] are
not decoded, while address bits [31:16] must be equal to 0, which means that these
addresses are aliases every 1KB throughout the first 64KB of I/O space.
Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C8152x behaves in the
same way as if only the VGA mode bit were set.
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C8152x complies with the ordering rules
set forth in the PCI Local Bus Specification, Revision 2.2, for transactions crossing the
bridge. This chapter describes the ordering rules that control transaction forwarding across
PI7C8152x.
TRANSACTIONS GOVERNED BY ORDERING RULES
Ordering relationships are established for the following classes of transactions crossing
PI7C8152x:
Posted write transactions, comprised of memory write and memory write and
invalidate transactions.
Posted write transactions complete at the source before they complete at the destination;
that is, data is written into intermediate data buffers before it reaches the target.
Page 42 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B