PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 15

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.3
2.2.4
CLOCK SIGNALS
MISCELLANEOUS SIGNALS
Name
S_PERR_L
S_SERR_L
S_REQ_L[3:0]
S_GNT_L[3:0]
S_RESET_L
S_CFN_L
Name
P_CLK
S_CLKIN
S_CLKOUT[4:0]
Name
P_VIO
Pin #
4
3
42, 39, 38, 37
47, 45, 44, 43
48
49
Pin #
66
51
61, 59, 57, 55, 53
Pin #
67
Page 15 of 90
Type
Type
Type
STS
TS
O
O
I
I
I
I
I
I
Description
Secondary Parity Error (Active LOW): Asserted
when a data parity error is detected for data received on
the secondary interface. Before being tri-stated, it is
driven to a de-asserted state for one cycle.
Secondary System Error (Active LOW): Can be
driven LOW by any device to indicate a system error
condition.
Secondary Request (Active LOW): This is asserted by
an external device to indicate that it wants to start a
transaction on the secondary bus. The input is externally
pulled up through a resistor to VDD.
Secondary Grant (Active LOW): PI7C8152x asserts
these pins to allow external masters to access the
secondary bus. PI7C8152x de-asserts these pins for at
least 2 PCI clock cycles before asserting it again.
During idle and S_GNT_L deasserted, PI7C8152x will
drive S_AD, S_CBE, and S_PAR.
Secondary RESET (Active LOW): Asserted when any
of the following conditions are met:
1.
2.
When asserted, all control signals are tri-stated and
zeroes are driven on S_AD, S_CBE, and S_PAR.
Secondary Bus Central Function Control Pin: When
tied LOW, it enables the internal arbiter. When tied
HIGH, an external arbiter must be used. S_REQ_L[0] is
reconfigured to be the secondary bus grant input, and
S_GNT_L[0] is reconfigured to be the secondary bus
request output.
Description
Primary Clock Input: Provides timing for all
transactions on the primary interface.
Secondary Clock Input: Provides timing for all
transactions on the secondary interface.
Secondary Clock Output: Provides secondary clocks
phase synchronous with the P_CLK.
In synchronous mode, one of the clock outputs must be
fed back to S_CLKIN. Unused outputs may be disabled
by:
1. Writing the secondary clock disable bits in the
configuration space
2. Terminating them electrically.
In asynchronous mode, these pins may not be used.
Devices on the secondary interface should use the same
clock source that is used for S_CLKIN.
Description
Primary I/O Voltage: This pin is used to determine
either 3.3V or 5V signaling on the primary bus. P_VIO
must be tied to 3.3V only when all devices on the
primary bus use 3.3V signaling. Otherwise, P_VIO is
tied to 5V.
Signal P_RESET_L is asserted.
Secondary reset bit in bridge control register in
configuration space is set.
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B