PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 52

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3
Table 6-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT
Table 6-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT
Assertion of P_SERR_L is used to signal the parity error condition when the initiator does
not know that the error occurred. Because the data has already been delivered with no
errors, there is no other way to signal this information back to the initiator.
If the parity error has forwarded from the initiating bus to the target bus, P_SERR_L will
not be asserted.
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C8152x to data parity errors are presented
according to the type of transaction in progress. This section organizes the responses of
PI7C8152x to data parity errors according to the status bits that PI7C8152x sets and the
signals that it asserts.
Table 6-1 shows setting the detected parity error bit in the status register, corresponding to
the primary interface. This bit is set when PI7C8152x detects a parity error on the primary
interface.
Table 6-2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C8152x detects a parity
error on the secondary interface.
Primary Detected
Parity Error Bit
0
0
1
0
1
0
0
0
1
0
0
0
X = don’t care
Secondary
Detected
Error Bit
0
1
!
!
Parity
The parity error response bit is set in the command register of the primary
interface.
PI7C8152x has not detected the parity error on the secondary (initiator) bus,
which the parity error is not forwarded from the secondary bus to the
primary bus.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Page 52 of 90
Direction
Downstream
Upstream
Direction
Downstream
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
Was Detected
Was Detected
ADVANCE INFORMATION
PI7C8152A & PI7C8152B
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary/
Primary/
Bits
Bits