PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 81

• Manufacturer Part Number: PI7C8152BMAE
• Description: IC PCI-PCI BRIDGE 2PORT 160-MQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8152BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 246 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.1.34
12.1.35
P_SERR_L STATUS REGISTER – OFFSET 68h
PORT OPTION REGISTER – OFFSET 74h
Bit
7:6
8
13:9
15:14
Bit
16
17
18
19
20
21
22
23
Bit
0
Function
Clock 3 disable
Clock 4 disable
Reserved
Reserved
Function
Address Parity
Error
Posted Write
Data Parity Error
Posted Write
Non-delivery
Target Abort
during Posted
Write
Master Abort
during Posted
Write
Delayed Write
Non-delivery
Delayed Read –
No Data from
Target
Delayed
Transaction
Master Timeout
Function
Reserved
Type
R/W
R/W
RO
RO
Type
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
Type
R/O
Page 81 of 90
Description
S_CLKOUT[3] (slot 3) Enable
00: enable S_CLKOUT[3]
01: enable S_CLKOUT[3]
10: enable S_CLKOUT[3]
11: disable S_CLKOUT[3] and driven HIGH
Reset to 00
S_CLKOUT[4] (device 1) Enable
0: enable S_CLKOUT[4]
1: disable S_CLKOUT[4] and driven HIGH
Reset to 0
Reserved. Reset to 1Fh
Reserved. Reset to 00
Description
1: Signal P_SERR_L was asserted because an address parity error
was detected on P or S bus.
Reset to 0
1: Signal P_SERR_L was asserted because a posted write data parity
error was detected on the target bus.
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver post memory write data to the target after 2
Reset to 0
1: Signal P_SERR_L was asserted because the bridge received a
target abort when delivering post memory write data.
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge received a
master abort when attempting to deliver post memory write data
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver delayed write data after 2
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
read any data from the target after 2
Reset to 0.
1: Signal P_SERR_L was asserted because a master did not repeat a
read or write transaction before master timeout.
Reset to 0.
Description
Reserved. Returns 0 when read. Reset to 0.
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
24
attempts.
24
PI7C8152A & PI7C8152B
attempts.
24
attempts.