LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 102

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
20 TIMING DIAGRAMS FOR SER_IRQ CYCLE
A) Start Frame timing with source sampled a low pulse on IRQ1
Note:
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge
B) Stop Frame Timing with Host using 17 SER_IRQ sampling period.
Note:
Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-
Note 2: There may be none, one or more Idle states during the Stop Frame.
Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
SMSC DS – LPC47M112
PCI_CLK
SER_IRQ
Drive Source
PCI_CLK
SER_IRQ
Driver
H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
hierarchy in a synchronous bridge design.
H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
around clock of the Stop Frame.
S
FRAME
None
IRQ14
R
IRQ1
SL
or
H
T
START
Host Controller
S
START FRAME
H
IRQ15
IRQ15
FRAME
R
1
T
DATASHEET
R
S
IOCHCK#
None
FRAME
T
R
Page 102
IRQ0 FRAME IRQ1 FRAME
T
S
None
I
R
2
STOP FRAME
Host Controller
T
STOP
H
S
1
IRQ1
R
R
T
T
NEXT CYCLE
IRQ2 FRAME
S
None
START
R
3
T
Rev. 02-16-07