LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 94

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
BITS 7,6,5
These bits are Read/Write and select the Mode.
BIT 4 nErrIntrEn
Read/Write (Valid only in ECP Mode)
1:
0:
BIT 3 dmaEn
Read/Write
1:
0:
BIT 2 serviceIntr
Read/Write
1:
0:
case dmaEn=1:
case dmaEn=0 direction=0:
case dmaEn=0 direction=1:
BIT 1 full
Read only
1:
0:
BIT 0 empty
Read only
1:
0:
SMSC DS – LPC47M112
Disables the interrupt generated on the asserting edge of nFault.
Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is
asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time
between the read of the ecr and the write of the ecr.
Enables DMA (DMA starts when serviceIntr is 0).
Disables DMA unconditionally.
Disables DMA and all of the service interrupts.
Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit
shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause
an interrupt.
During DMA (this bit is set to a 1 when terminal count is reached).
This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO.
This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO.
The FIFO cannot accept another byte or the FIFO is completely full.
The FIFO has at least 1 free byte.
The FIFO is completely empty.
The FIFO contains at least 1 byte of data.
R/W
000:
001:
010:
011:
100:
101:
110:
111:
Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are
used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will
not tri-state the output drivers in this mode.
PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the
data lines and reading the data register returns the value on the data lines and not the value in
the data register. All drivers have active pull-ups (push-pull).
Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the
FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that
this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull).
ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo
and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to
the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved
from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active
pull-ups (push-pull).
Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in
configuration register L3-CRF0. All drivers have active pull-ups (push-pull).
Reserved
Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted
on the parallel port. All drivers have active pull-ups (push-pull).
Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and
0x401. All drivers have active pull-ups (push-pull).
Table 44A - Extended Control Register
DATASHEET
Page 94
MODE
Rev. 02-16-07