LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 167

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
Note 1: This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the
Note 2: The Configuration Port is at either 0x02E or 0x04E (for SYSOPT=0 or SYSOPT=1) at power up and can be
Note:
Note:
Note:
Note:
Note 1: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
SMSC DS – LPC47M112
Primary Interrupt
Select
Default=0x00 or
0x06
on VCC POR,
VTR POR,
HARD RESET
and
SOFT RESET
LOGICAL
NUMBER
OSC Global Configuration Register (CR24) must be set to ‘1’ and Address Bits [A15:A12] must be ‘0’ for 16 bit
address qualification.
replaced via the global configuration registers at 0x26 and 0x27.
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND :
And by setting the OUT2 bit in the UART's Modem Control (MCR) Register.
IRQs are disabled if not used/selected by any Logical Device. Refer to Note A.
All IRQ’s are available in Serial IRQ mode.
nSMI must be disabled to use IRQ2.
DEVICE
Config.
Port
NAME
(Note 1)
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
For the Serial Port logical device by setting any combination of bits D0-D3 in the IER
For the KYBD by (refer to the KYBD controller section of this spec).
Config. Port
LOGICAL
DEVICE
Table 64 - Interrupt Select Configuration Register Description
0x70 (R/W)
REG INDEX
REGISTER
0x26, 0x27
(Note 2)
INDEX
Bits[3:0] selects which interrupt is used for the primary
Interrupt.
Note: All interrupts are edge high (except ECP/EPP)
Note: nSMI is active low
DATASHEET
0x00= no interrupt selected
0x01= IRQ1
0x02= IRQ2/nSMI
0x03= IRQ3
0x04= IRQ4
0x05= IRQ5
0x06= IRQ6
0x07= IRQ7
0x08= IRQ8
0x09= IRQ9
0x0A= IRQ10
0x0B= IRQ11
0x0C= IRQ12
0x0D= IRQ13
0x0E= IRQ14
0x0F= IRQ15
Page 167
On 2 byte boundaries
0x0100:0x0FFE
BASE I/O
(NOTE 1)
RANGE
DEFINITION
See Configuration
Registers in Table 54.
Accessed through the
index and DATA ports
located at the
Configuration Port
address and the
Configuration Port
address +1 respectively.
BASE OFFSETS
FIXED
STATE
C
Rev. 02-16-07