LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 109

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
Status Register
This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M112 CPU.
UD
C/D
IBF
OBF
EXTERNAL CLOCK SIGNAL
The LPC47M112 Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset
pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR)
and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip.
DEFAULT RESET CONDITIONS
The LPC47M112 has one source of hardware reset: an external reset via the nPCI_RESET pin. Refer to Table 46 for
the effect of each type of reset on the internal registers.
SMSC DS – LPC47M112
Writable by LPC47M112 CPU. These bits are user-definable.
(Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1 =
command). During a host data/command write operation, this bit is set to "1" if SA2 = 1 or reset to "0" if SA2 =
0.
(Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register.
Setting this flag activates the LPC47M112 CPU's nIBF (MIRQ) interrupt if enabled. When the LPC47M112
CPU reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no
output pin associated with this internal signal.
(Output Buffer Full) - This flag is set to whenever the LPC47M112 CPU write to the output data register (DBB).
When the host system reads the output data register, this bit is automatically reset.
UD
D7
KCLK
KDAT
MCLK
MDAT
Host I/F Data Reg
Host I/F Status Reg
UD
D6
DESCRIPTION
UD
D5
DATASHEET
Table 51 - Status Register
N/A: Not Applicable
Table 52 - Resets
UD
D4
Page 109
C/D
D3
HARDWARE RESET
(nPCI_RESET)
00H
Low
Low
Low
Low
N/A
UD
D2
IBF
D1
OBF
D0
Rev. 02-16-07