LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 158

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
Notes: HARD RESET: nPCI_RESET pin asserted
SMSC DS – LPC47M112
SOFT RESET: Bit 0 of Configuration Control register set to one
All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram)
INDEX
0x60,
0x60,
0x2A
0x2B
0x2C
0x2D
0x2E
0x02
0x03
0x07
0x20
0x21
0x22
0x23
0x24
0x26
0x27
0x28
0x2F
0x30
0x61
0x70
0x74
0xF0
0xF1
0xF2
0xF4
0xF5
0x30
0x61
0x70
0x74
0xF0
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port)
LOGICAL DEVICE 1 CONFIGURATION REGISTERS (Reserved)
LOGICAL DEVICE 2 CONFIGURATION REGISTERS (Reserved)
Table 60 – LPC47M112 Configuration Registers Summary
LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD)
0x00
Sysopt=0:
Sysopt=1:
Sysopt=0:
Sysopt=1:
RESET
HARD
0x03,
0x00,
0x3C
0x00
0x00
0x59
0x00
0x00
0x44
0x2E
0x4E
0x00
0x00
0x00
0xF0
0x06
0x02
0x0E
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0x04
-
-
-
-
-
-
-
-
(Note 1)
GLOBAL CONFIGURATION REGISTERS
DATASHEET
VCC POR
0x00
Sysopt=0:
Sysopt=1:
Sysopt=0:
Sysopt=1:
0x03,
0x00,
0x3C
0x2E
0x4E
0xF0
0x0E
0xFF
0x00
0x00
0x59
0x00
0x00
0x44
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x06
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x04
-
-
(Note 1)
Page 158
0x00
VTR POR
0x03,
0x00,
0x0E
0xFF
0x3C
0x00
0x00
0x59
0x00
0x00
0x44
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xF0
0x06
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x04
-
-
-
-
(Note 1)
0x00
RESET
SOFT
0x03,
0x00,
0x00
0x59
0x00
0x00
0xF0
0x06
0x02
0x00
0x00
0x00
0x04
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(Note 1)
Config Control
Reserved
return 0
Logical
Number
Device ID - hard wired
Device Rev - hard
wired
Power Control
Power Mgmt
OSC
Configuration
Address Byte 0
(Low Byte)
Configuration
Address Byte 1
(High Byte)
Reserved
TEST 6
TEST 4
TEST 5
TEST 1
TEST 2
TEST 3
Activate
Primary
Address
Primary
Select
DMA Channel Select
FDD Mode Register
FDD Option Register
FDD Type Register
FDD0
FDD1
Activate
Primary
Address
Primary
Select
DMA Channel Select
Parallel
Register
CONFIGURATION
REGISTER
Port
Base
Base
–
Interrupt
Interrupt
Device
reads
Mode
Port
Port
Rev. 02-16-07
I/O
I/O