LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 171

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
Note 1: To properly share and IRQ,
assert when either UART generates an interrupt.
SMSC DS – LPC47M112
Note: If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs will
Serial Port 1
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
Serial Port 2
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
1. Configure UART1 (or UART2) to use the desired IRQ.
2. Configure UART2 (or UART1) to use No IRQ selected.
3. Set the share IRQ bit.
NAME
NAME
Table 67 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04]
Table 68 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]
REG INDEX
REG INDEX
0xF0 R/W
0xF0 R/W
Bit[0] MIDI Mode
= 0
= 1
Bit[1] High Speed
= 0
= 1
Bit[6:2] Reserved, set to zero
Bit[7]: Share IRQ
=0 UARTS use different IRQs
=1 UARTS share a common IRQ
See Note 1 below.
Bit[0] MIDI Mode
= 0
= 1
Bit[1] High Speed
= 0
= 1
Bit[4:2] Reserved, set to zero
Bit[5] TXD2_MODE (Note 1)
=0
=1
Bits[7:6] Reserved. Set to zero.
DATASHEET
UART Interrupt Operation
MIDI support disabled (default)
MIDI support enabled
High Speed Disabled(default)
High Speed Enabled
MIDI support disabled (default)
MIDI support enabled
High Speed disabled(default)
High Speed enabled
The inactive state of the TXD2 pin is low
The state of the TXD2 pin is tristate
Page 171
DEFINITION
DEFINITION
STATE
STATE
C
C
Rev. 02-16-07