LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 72

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
ADDR = 6
Enhanced Super I/O Controller with LPC Interface
Datasheet
SMSC DS – LPC47M112
ADDRESS*
REGISTER
Interrupt Enable Register
Interrupt Identification Reg.
FIFO Control
Line Control Reg.
MODEM Control Reg.
Line Status Reg.
MODEM Status Reg.
TXD1, TXD2
INTRPT (RCVR errs)
INTRPT (RCVR Data Ready)
INTRPT (THRE)
OUT2B
RTSB
DTRB
OUT1B
RCVR FIFO
XMIT FIFO
REGISTER/SIGNAL
Receive Buffer Register (Read Only)
Transmitter Holding Register (Write
Only)
Interrupt Enable Register
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
Table 32 - Register Summary for an Individual UART Channel
REGISTER NAME
RESET CONTROL
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET/Read LSR
RESET/Read RBR
RESET/ReadIIR/Write THR
RESET
RESET
RESET
RESET
RESET/
FCR1*FCR0/_FCR0
RESET/
FCR1*FCR0/_FCR0
Table 31 - Reset Function
DATASHEET
Page 72
FCR
REGISTER
SYMBOL
MCR
MSR
RBR
THR
LCR
LSR
IER
IIR
(Note 7)
All bits low
Bit 0 is high; Bits 1 - 7 low
All bits low
All bits low
All bits low
All bits low except 5, 6 high
Bits 0 - 3 low; Bits 4 - 7 input
High
Low
Low
Low
High
High
High
High
All Bits Low
All Bits Low
RESET STATE
Data
(Note 1)
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERDAI)
"0" if Interrupt
Pending
Word Length
Select Bit 0
(WLS0)
Data Terminal
Ready (DTR)
Data Ready
(DR)
Delta Clear to
Send (DCTS)
FIFO Enable
BIT 0
Bit
0
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID
Bit
RCVR FIFO
Reset
Word Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Overrun Error
(OE)
Delta Data
Set Ready
(DDSR)
BIT 1
Rev. 02-16-07