LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 62

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
12 SERIAL PORT (UART)
The LPC47M112 incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE
registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to-
serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to
50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and
prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input
clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to
the Configuration Registers for information on disabling, power down and changing the base address of the UARTs.
The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0"
disables that UART's interrupt. The second UART also supports IrDA, HP-SIR and ASK-IR modes of operation.
Note: The UARTs 1 and 2 may be configured to share an interrupt. Refer to the Configuration section for more
information.
REGISTER DESCRIPTION
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are
defined by the configuration registers (see Configuration section). The Serial Port registers are located at sequentially
increasing addresses above these base addresses. The LPC47M112 contains two serial ports, each of which contain a
register set as described below.
The following section describes the operation of the registers.
RECEIVE BUFFER REGISTER (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received
first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert
it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible.
TRANSMIT BUFFER REGISTER (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift
register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit
Buffer when the transmission of the previous byte is complete.
SMSC DS – LPC47M112
*Note: DLAB is Bit 7 of the Line Control Register
DLAB*
X
X
X
X
X
X
X
0
0
0
1
1
A2
0
0
0
0
0
0
1
1
1
1
0
0
Table 28 - Addressing the Serial Port
A1
0
0
0
0
1
0
0
1
1
1
0
1
DATASHEET
A0
0
0
1
0
0
1
0
1
0
1
0
1
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
Page 62
REGISTER NAME
Rev. 02-16-07