LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 20

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
8
8.1 Super I/O Registers
The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately
after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and
configuration register block can be moved via the configuration registers. Some addresses are used to access more
than one register.
8.2 Host Processor Interface (LPC)
The host processor communicates with the LPC47M112 through a series of read/write registers via the LPC interface.
The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or
DMA transfers. All registers are 8 bits wide.
8.3 LPC INTERFACE
The following sub-sections specify the implementation of the LPC bus.
8.3.1
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz
electrical signal characteristics.
SMSC DS – LPC47M112
FUNCTIONAL DESCRIPTION
LAD[3:0]
nLFRAME
nPCI_RESET
nLDRQ
nIO_PME
nLPCPD
SER_IRQ
SIGNAL NAME
Note:
LPC INTERFACE SIGNAL DEFINITION
Refer to the configuration register descriptions for setting the base address.
Base+(0-5) and +(7)
Base+(0-7)
Base1+(0-7)
Base2+(0-7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
60, 64
Base + 0
Base + (0-5F)
Base + (0-7)
Base + (0-1)
Output
TYPE
Input
Input
Input
OD
I/O
I/O
ADDRESS
LPC address/data bus. Multiplexed command, address and data bus.
Encoded DMA/Bus Master request for the LPC interface.
Frame signal. Indicates start of new cycle and termination of broken
cycle
PCI Reset.
RST_DRV but active low 3.3V.
Power Mgt Event signal. Allows the LPC47M112 to request wakeup.
Powerdown Signal. Indicates that the LPC47M112 should prepare for
power to be shut on the LPC interface.
Serial IRQ.
Table 1 - Super I/O Block Addresses
DATASHEET
Used as LPC Interface Reset. Same functionality as
Floppy Disk
Serial Port Com 1
Serial Port Com 2
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
KYBD
Game Port
Runtime Registers
MPU-401
Configuration
BLOCK NAME
Page 20
DESCRIPTION
LOGICAL DEVICE
A
B
0
4
5
3
7
9
Rev. 02-16-07