LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 134

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
Note 1: This register is read-only when GP43 register bit [3:2] = 01 and the GP43 pin is high.
Note 2: Bits [3:2] of this register are reset (cleared) on VCC POR and Hard Reset (and VTR POR).
Note 3: Bit 3 of this register is reset (cleared) on VCC POR and Hard Reset (and VTR POR).
Note 4: The parallel port interrupt defaults to 1 when the parallel port activate bit is cleared.
Note 5: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register may be set on a
The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address
register for Logical Device A.
SMSC DS – LPC47M112
PME_STS
Default = 0x00
on VTR POR
N/A
PME_EN
Default = 0x00
on VTR POR
N/A
REGISTER
VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI status
bits will be set on a VCC POR since these pins revert to their non-inverting GPIO output function when VCC
is removed from the part. These GPIOs cannot be used for PME wakeup when the part is under VTR power
(VCC=0).
OFFSET
60-7F
(hex)
5D
5E
5F
NAME
TYPE
R/W
R/W
R/W
R
REG OFFSET
RESET
HARD
(R/W)
(R/W)
(hex)
Table 58 - Runtime Register Description
-
-
-
-
(R)
(R)
00
01
02
03
DATASHEET
POR
VCC
-
-
-
-
Bit[0] PME_Status
= 0 (default)
= 1 Set when LPC47M112 would normally assert the
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET or
HARD RESET.
Writing a “1” to PME_Status will clear it and cause the
LPC47M112 to stop asserting nIO_PME, in enabled.
Writing a “0” to PME_Status has no effect.
Reserved – reads return 0
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or
HARD RESET
Reserved – reads return 0
nIO_PME signal, independent of the state of the
PME_En bit.
Page 134
VTR POR
nIO_PME signal assertion is disabled (default)
Enables LPC47M112 to assert nIO_PME signal
0x00
0x00
0x00
-
RESET
SOFT
-
-
-
-
DESCRIPTION
LED1
LED2
Reserved – reads return 0
Keyboard Scan Code
REGISTER
Rev. 02-16-07