LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 203

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
Introduction
The LPC47M112 provides board test capability through the XNOR chain. When the chip is in the XNOR chain test
mode, setting the state of any of the input pins to the opposite of its current state will cause the output of the chain to
toggle.
All pins on the chip are inputs to the XNOR chain, with the exception of the following:
1)
2)
3)
4)
To put the chip in the XNOR chain test mode, tie LAD0 (pin 20) and nLFRAME (pin 24) low.
nPCI_RESET (pin 26) from a low to a high state. Once the chip is put into XNOR chain test mode, LAD0 (pin 20) and
nLFRAME (pin 24) become part of the chain.
To exit the XNOR chain test mode tie LAD0 (pin 20) or nLFRAME (pin 24) high. Then toggle nPCI_RESET (pin 26)
from a low to a high state. A VCC POR will also cause the XNOR chain test mode to be exited. To verify the test
mode has been exited, observe the output at FAN_TACH1 (pin 52). Toggling any of the input pins should not cause
its state to change.
1)
2)
3)
4)
Testing
1)
2)
3)
4)
5)
6)
7)
SMSC DS – LPC47M112
Setup
VCC (pins 53, 65 & 93), VTR (pin 18), and VREF (pin 44).
VSS (pins 7, 31, 60, & 76) and AVSS (pin 40).
FAN_TACH1 (pin 52). This is the chain output.
nPCI_RESET (pin 26).
Connect VSS (pins 7, 31, 60, & 76) and AVSS (pin 40) to ground.
Connect VCC (pins 53, 65 & 93), VTR (pin 18), and VREF (pin 44) to VCC (3.3V).
Connect an oscilloscope or voltmeter to FAN_TACH1 (pin 52).
All other pins should be tied to ground.
Turn power on.
With LAD0 (pin 20) and nLFRAME (pin 24) low, bring nPCI_RESET (pin 26) high. The chip is now in XNOR
chain test mode. At this point, all inputs to the XNOR chain are low. The output, on FAN_TACH1 (pin 52), should
also be low. Refer to INITIAL CONFIG on Truth Table 1.
Bring pin 100 high. The output on FAN_TACH1 (pin 52) should go high. Refer to STEP ONE on Truth Table 1.
In descending pin order, bring each input high. The output should switch states each time an input is toggled.
Continue until all inputs are high. The output on FAN_TACH1 should now be low. Refer to END CONFIG on
Truth Table 1.
The current state of the chip is now represented by INITIAL CONFIG in Truth Table 2.
Each input should now be brought low, starting at pin one and continuing in ascending order. Continue until all
inputs are low. The output on FAN_TACH1 should now be low. Refer to Truth Table 2.
To exit test mode, tie LAD0 (pin 20) OR nLFRAME (pin 24) high, and toggle nPCI_RESET from a low to a high
state.
Warning: Ensure power supply is off during setup.
DATASHEET
Page 203
Then toggle
Rev. 02-16-07