LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 29

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
BIT 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and
interrupt functions. This bit is a logic "0" after a reset and in these modes.
PS/2 Mode:
In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic "0".
BIT 4 MOTOR ENABLE 0
This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.
BIT 5 MOTOR ENABLE 1
This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.
BIT 6 MOTOR ENABLE 2
The MTR2 disk interface output is not supported in the LPC47M112.
BIT 7 MOTOR ENABLE 3
The MTR3 disk interface output is not supported in the LPC47M112.
TAPE DRIVE REGISTER (TDR)
Address 3F3 READ/WRITE
The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support
to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR
Tape Select bits TDR.[1:0] determine the tape drive number. Table 3 illustrates the Tape Select Bit encoding. Note that
drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are
tristated when read. The TDR is unaffected by a software reset.
SMSC DS – LPC47M112
Bit 7
X
X
X
1
0
DIGITAL OUTPUT REGISTER
Bit 6
X
X
X
1
0
Bit 5
X
X
X
1
0
Bit 4
X
X
X
0
1
TAPE SEL1
Table 4 - Internal 2 Drive Decode - Normal
(TDR.1)
Bit1
X
0
0
1
1
0
0
1
1
DRIVE
DATASHEET
Table 3 - Tape Select Bits
Bit 0
0
1
0
1
0
1
X
TAPE SEL0
DRIVE SELECT OUTPUTS
(TDR.0)
Page 29
nDS1
0
1
0
1
1
0
1
1
1
(ACTIVE LOW)
DOR VALUE
1CH
2DH
SELECTED
nDS0
DRIVE
None
0
1
1
1
1
1
2
3
MOTOR ON OUTPUTS
nMTR1
nBIT 5
nBIT 5
nBIT 5
nBIT 5
nBIT 5
(ACTIVE LOW)
nMTR0
nBIT 4
nBIT 4
nBIT 4
nBIT 4
nBIT 4
Rev. 02-16-07