LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 23

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
If the host was reading data from the LPC47M112, data will still be transferred in the next two nibbles. This data may
be invalid, but it will be transferred by the LPC47M112. If the host was writing data to the LPC47M112, the data had
already been transferred.
8.4.5.1
In the case of multiple byte cycles, such as memory and DMA cycles, an error SYNC terminates the cycle. Therefore,
if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three
bytes will not be transferred.
8.4.5.2
I/O and DMA cycles use a START field of 0000.
8.4.5.3
The following rules govern the reset policy:
1)
2)
8.4.5.4
The LPC interface uses 3.3V signaling. No output from the LPC47M112 drives higher than 3.3V nominal.
The electrical characteristics of each signal is described below.
8.4.5.4.1
The AC and DC specifications for these signals are the same as defined for AD[31:0] in section 4.2.2 of the “PCI
Local Bus Specification, Rev 2.1”. That section contains the specifications for the 3.3V signaling environment.
The LAD[3:0] signals go high during the TAR phase. The last device driving the LAD[3:0] is responsible to drive the
signals high during the first clock of the TAR phase. During the second clock, neither the host nor the LPC47M112
will drive LAD[3:0] (LAD[3:0] is floated).
Weak pull-up resistors of 10k-100k ohms will be included on LAD[3:0] to keep the signals high. These pull-ups are
external to the LPC47M112.
8.4.5.4.2
The AC and DC specifications for these signals are the same as for non-shared signals as defined in section 4.2.2 of
the “PCI Local Bus Specification, Rev 2.1”.
environment.
nLDRQ is a standard output from the LPC47M112 and a standard input to the host.
8.4.5.4.3
The host drives this signal as a standard 3.3V output.
8.4.5.4.4
The host drives this signal as a standard 3.3V output.
8.4.5.4.5
The host drives this signal as a standard 3.3V output.
SMSC DS – LPC47M112
When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec prior to the
removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable
that is used for the PCI bus.
When nPCI_RESET goes active (low):
a)
b)
the host drives the nLFRAME signal high, tristates the LAD[3:0] signals, and ignores the nLDRQ signal.
the LPC47M112 must ignore nLFRAME, tristate the LAD[3:0] pins and drive the nLDRQ signal inactive
(high).
I/O and DMA START Fields
Reset Policy
Electrical Specifications
LAD[3:0]
nLDRQ
nLPCPD
nLFRAME
nPCI_RESET
DATASHEET
That section contains the specifications for the 3.3V signaling
Page 23
Rev. 02-16-07