LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 125

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
25 FAN SPEED CONTROL AND MONITORING
The LPC47M112 implements fan speed control outputs and fan tachometer inputs. The implementation of these
features are described in the sections below.
25.1
The fan speed control for the LPC47M112 is implemented as pulse width modulators with fan clock speed selection.
Pins 54 and 55 are the fan speed control outputs, FAN2 and FAN1, respectively, muxed with GPIOs. These fan
control pins come up as outputs and are low following a VCC POR and Hard Reset. These pins may not be used for
wakeup events under VTR power (VCC=0).
The configuration registers are defined in the “Runtime Registers” section.
Fan Speed Control Summary
The following table illustrates the different modes for the fans.
Note 1: This is FANx Register Bit 0
Note 2: This is Fan Control Register Bit 2 or 3
Note 3: This is Fan Control Register Bit 0 or 1
Note 4: This is FANx Register Bit 7
25.1.1 FANX REGISTERS
The FAN1 and FAN2 Registers are located at 0x56 and 0x57 from base I/O in Logical Device A. The bits are defined
below. See the register description in the Runtime Registers section.
25.1.1.1
The Fan x Clock Select bit in the FANx registers is used with the Fan x Clock Source Select and the Fan x Clock
Multiplier bits in the Fan Control register to determine the fan speed F
25.1.1.2
The Duty Cycle Control (DCC) bits determine the fan duty cycle. The LPC47M112 has ≈1.56% duty cycle resolution.
When DCC = “000000” (min. value), F
high; i.e., high for 63/64
Generally, the F
25.1.1.3
The Fan x Clock Control bit D0 is used to override the Duty Cycle Control for Fan x bits and force F
SMSC DS – LPC47M112
Fan Speed Control
(Note 1)
Control
Clock
FANx
Fan x Clock Select Bit, D7
Duty Cycle Control for Fan x, Bits D6 – D1
Fan x Clock Control, Bit D0
Bit
0
0
0
0
0
0
0
0
0
1
OUT
duty cycle (%) is (DCC ÷ 64) × 100.
Multiplier
(Note 2)
th
Clock
FANx
and low for 1/64
Bit
X
X
0
0
0
0
1
1
1
1
Select Bit
(Note 3)
OUT
Source
Clock
FANx
Table 56 – Different Modes for Fan
th
X
0
0
1
1
0
0
1
1
X
is always low. When DCC is “111111” (max. value), F
of the F
DATASHEET
OUT
Select Bit
(Note 4)
FANx
Clock
period.
Page 125
X
0
1
0
1
0
1
0
1
X
0Hz – LOW
15.625kHz
23.438kHz
40Hz
60Hz
31.25kHz
46.876kHz
80Hz
120Hz
0Hz – HIGH
F
OUT
out
. See Table 58 above.
6-Bit Duty
bits[6:1]
Control
(DCC)
Cycle
1-63
0
-
Duty Cycle
OUT
(DCC/64)
OUT
• 100
(%)
is almost always
-
-
always high.
Rev. 02-16-07