LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 119

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
The following table summarizes the PME and SMI functionality for each GPIO.
Triggered Interrupt (EETI) input capability for the GPIOs and the power source for the buffer on the I/O pads.
Note 1: GP35 and GP53 have the IRTX function and their output buffers are powered by VTR so that the pins are
Note 2: GP36-GP37 and GP40 should not be connected to any VTR powered external circuitry. These pins are not
Note 3: GP60 and GP61 have LED functionality which must be active under VTR so its buffer is powered by VTR.
Note 4: These pins can be used for wakeup events to generate a PME while the part is under VTR power (VCC=0).
Note 5: These pins cannot be used for wakeup events to generate a PME while the part is under VTR power
Note 6: GP43 defaults to the GPIO function on VCC POR and Hard Reset.
22.2
Six GPIO pins are implemented such that they allow an interrupt (PME or SMI) to be generated on both a high-to-low
and a low-to-high edge transition, instead of one or the other as selected by the polarity bit.
The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the GPIO pin, then
the bits that control input/output, polarity and open collector/push-pull have no effect on the function of the pin.
However, the polarity bit does affect the value of the GP bit (i.e., register GP2, bit 2 for GP22).
A PME or SMI interrupt occurs if the PME or SMI enable bit is set for the corresponding GPIO and the EETI function
is selected on the GPIO. The PME or SMI status bits are set when the EETI pin transitions (on either edge) and are
cleared on a write of ‘1’. There are also status bits for the EETIs located in the MSC_STS register, which are also
cleared on a write of ‘1’. The MSC_STS register provides the status of all of the EETI interrupts within one register.
The PME, SMI or MSC status is valid whether or not the interrupt is enabled and whether or not the EETI function is
selected for the pin.
Miscellaneous Status Register (MSC_STS) is for the either edge triggered interrupt status bits. If the EETI function is
selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding MSC status bits.
Status bits are cleared on a write of ‘1’. See Runtime Register section for more information.
22.3
The LPC47M112 provides LED functionality on two GPIOs, GP60 and GP61. These pins can be configured to turn
the LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at offset 0x5D
and 0x5E from the base address located in the primary base I/O address in Logical Device A.
SMSC DS – LPC47M112
GP10-GP17
GP20-GP22, GP24-GP26
GP27
GP30, GP31
GP32, GP33
GP35
GP36, GP37
GP40
GP41
GP42
GP43
GP50-GP52
GP53
GP54-GP57
GP60, GP61
always forced low when not used.
used for wakeup.
(VCC=0). The GP32, GP33 and GP53 pins come up as output and low on a VCC POR and hard reset.
These pins revert to their non-inverting GPIO output function when VCC is removed from the part.
Either Edge Triggered Interrupts
Led Functionality
GPIO
nIO_PME
PME
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
DATASHEET
nIO_SMI
Page 119
SMI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
GP21, GP22
EETI
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
It also shows the Either Edge
BUFFER
POWER
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTR
VTR
VTR
VTR
NOTES
4, 6
1, 5
3, 4
4
4
4
4
5
1
2
2
4
4
4
Rev. 02-16-07