LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 137

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
SMSC DS – LPC47M112
PME_EN2
Default = 0x00
PME_EN3
Default = 0x00
on VTR POR
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(hex)
0B
0C
DATASHEET
PME Wake Enable Register 2
This register is used to enable individual LPC47M112 PME
wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source
is active (“1”), if the source asserts a wake event so that
the associated status bit is “1” and the PME_En bit is “1”,
the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source
is inactive (“0”), the PME Wake Status register will indicate
the state of the wake source but will not assert the
nIO_PME signal.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
PME Wake Status Register 3
This register is used to enable individual LPC47M112 PME
wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source
is active (“1”), if the source asserts a wake event so that
the associated status bit is “1” and the PME_En bit is “1”,
the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source
is inactive (“0”), the PME Wake Status register will indicate
the state of the wake source but will not assert the
nIO_PME signal.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] DEVINT_EN (Enable bit for group SMI signal for PME)
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP27
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Page 137
DESCRIPTION
Rev. 02-16-07