LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 79

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
17 BITS[5:0]
RESERVED (Reserved bits cannot be written and return ‘0’ when read).
Command Port
The Command port is used to transfer MPU-401 commands to the Command Controller. The Command port is write-
only (Table 38). See Section “MPU-401 Command Controller” below.
Interrupt
The MPU-401 IRQ is asserted (‘1’) when either MIDI receive data or a command acknowledge byte is available to the
host in the MIDI Data register (Figure 3). The IRQ is deasserted (‘0’) when the host reads the MIDI Data port.
NOTE: If, following a host read, data is still available in the Receive FIFO, the IRQ will remain asserted (‘1’).
The IRQ is enabled when the ‘Activate’ bit in the MPU-401 configuration registers logical device block is asserted ‘1’.
If the Activate bit is deasserted ‘0’, the MPU-401 IRQ cannot be asserted (see Section “MPU-401 Configuration
Registers”).
The MPU-401 IRQ is not affected by MIDI write data, transmit-related functions or Receiver Line Status interrupts.
The factory default Sound Blaster 16 MPU-401 IRQ is 5.
Note
Note
Note
Note
SMSC DS – LPC47M112
MIDI RX CLOCK
DATA READY
1
2
3
4
TYPE
NAME
DATA READY represents the Data Ready bit B0 in the UART Line Status Register.
nREAD represents host read operations from the MIDI Data register.
IRQ is the MPU-401 Host Interface IRQ shown in Figure 2. The UART Receive FIFO Threshold = 1.
MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32μs.
MIDI_IN
nREAD
IRQ
4
1
3
2
MPU-401 I/O BASE ADDRESS+1
D7
W
COMMAND REGISTER
MIDI RX DATA BYTE N
D6
W
D5
W
Table 38 – MPU-401 Command Port
FIGURE 3 - MPU-401 INTERRUPT
D4
W
DATASHEET
MIDI RX DATA BYTE N+1
D3
W
Page 79
D2
W
D1
W
D0
W
NOTE: IRQ remains asserted
until read FIFO is empty
DEFAULT
n/a
Rev. 02-16-07