LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 112

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
KLATCH Bit
VCC
KINT
new
D
Q
KINT
CLR
8042
RD 60
FIGURE 5 – KEYBOARD LATCH
MLATCH Bit
VCC
MINT
new
D
Q
MINT
CLR
8042
RD 60
FIGURE 6 – MOUSE LATCH
The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0.
These bits are defined as follows:
Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT (default),
1=MINT is the latched 8042 MINT.
Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched KINT (default),
1=KINT is the latched 8042 KINT.
SMSC DS – LPC47M112
Page 112
Rev. 02-16-07
DATASHEET