LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 33

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register
can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It
should be read before each byte transferring to or from the data register except in DMA mode. No delay is required
when reading the MSR after a data transfer.
BIT 0 - 1 DRV x BUSY
These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and
recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted
and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is
returned to a 0 after the last command byte.
BIT 5 NON-DMA
This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a command. This
is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
DATA REGISTER (FIFO)
Address 3F5 READ/WRITE
All command parameter information, disk data and result status are transferred between the host processor and the
floppy disk controller through the Data Register.
Data transfers are governed by the RQM and DIO bits in the Main Status Register.
The Data Register defaults to FIFO disabled mode after any form of reset.
compatibility. The default values can be changed through the Configure command (enable full FIFO operation with
threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk
error. Table 11 gives several examples of the delays with a FIFO.
The data is based upon the following formula:
At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the
RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that
invalid data is not transferred.
An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current
sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result
phase may be entered.
SMSC DS – LPC47M112
RQM
7
Threshold # x
DIO
6
NON
DMA
5
DATA RATE
DATASHEET
1
BUSY
CMD
4
Page 33
x 8
- 1.5 μs = DELAY
Reserved Reserved
3
2
This maintains PC/AT hardware
BUSY
DRV1
1
DRV0
BUSY
0
Rev. 02-16-07